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mos integrated circuit p p p p pd70f3017a, 70f3017ay v850/sa1 tm 32-/16-bit single-chip microcontroller document no. u14527ej2v0ds00 (2nd edition) date published august 2000 j cp(k) printed in japan data sheet ? 2000 the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. the mark shows major revised points. the p pd70f3017a, 70f3017ay are products with on-chip flash memory. because the devices can be programmed by the user on-board, they are ideal for the evaluation stages of system development, small-scale production of a variety of products, and rapid development of new products. the v850/sa1 provides a high-level cost performance ideal for applications ranging from low-power camcorders and other av equipment to portable telephone equipment such as cellular phones and personal handyphone systems (phs). detailed function descriptions are provided in the following user's manuals. be sure to read them before designing. v850/sa1 user's manual hardware: u12768e v850 family tm user's manual architecture: u10243e features { number of instructions: 74 { minimum instruction execution time: 59 ns (@ 17 mhz operation with main system clock (f xx )) 50 ns (@ 20 mhz operation with main system clock (f xx )) 30.5 p s (@ 32.768 khz operation with subsystem clock (f xt )) { general-purpose registers: 32 bits u 32 registers { instruction set: signed multiplication, saturation operations, 32-bit shift instructions, bit manipulation instructions, load/store instructions { memory space: 16 mb linear address space memory block division function: 2 mb per block { external bus interface: 16-bit data bus address bus: separate output enabled { internal memory flash memory: 256 kb ram: 8 kb { interrupts and exceptions external: 8, internal: 23, exceptions: 1 { i/o lines total: 85 { timer/counters 16-bit timer: 2 channels 8-bit timer: 4 channels { watch timer: 1 channel { watchdog timer: 1 channel { serial interface (sio) asynchronous serial interface (uart) clocked serial interface (csi) i 2 c bus interface ( p pd70f3017ay) { a/d converter: 12 channels { dma controller: 3 channels { rtp: 8 bits u 1 channel or 4 bits u 2 channels { power-saving functions: halt/idle/stop modes { packages: 100-pin plastic lqfp (14 u 14 mm) 121-pin plastic fbga (12 u 12 mm)
data sheet u14527ej2v0ds0 0 2 p pp p pd70f3017a, 70f3017ay applications { low-power portable devices cellular phones, phss, and camcorders ordering information part number package internal rom p pd70f3017agc-8eu p pd70f3017af1-ea6 p pd70f3017aygc-8eu p pd70f3017ayf1-ea6 100-pin plastic lqfp (fine-pitch) (1 4 u 14 mm) 121-pin plastic fbga (12 u 12 mm) 100-pin plastic lqfp (fine-pitch) (1 4 u 14 mm) 121-pin plastic fbga (12 u 12 mm) 256 kb (flash memory) 256 kb (flash memory) 256 kb (flash memory) 256 kb (flash memory)
data sheet u14527ej2v0ds00 3 p p p p pd70f3017a, 70f3017ay pin configuration 100-pin plastic lqfp (fine-pitch) (14 u 14 mm) p pd70f3017agc-8eu p pd70f3017aygc-8eu notes 1. connect the v pp pin to v ss in the normal operating mode. 2. applies to the p pd70f3017ay only. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 p20/si2 p15/sck1/asck0 p14/so1/txd0 p13/si1/rxd0 p12/sck0/scl note 2 p11/so0 p10/si0/sda note 2 p07/intp6 p06/intp5/rtptrg p05/intp4/adtrg p04/intp3 p03/intp2 p02/intp1 p01/intp0 p00/nmi p83/ani11 p82/ani10 p81/ani9 p80/ani8 p77/ani7 p76/ani6 p75/ani5 p74/ani4 p73/ani3 p72/ani2 p107/rtp7/a12 p110/a1 p111/a2 p112/a3 p113/a4 reset p114/xt1 xt2 v dd x2 x1 v ss clkout p120/wait p90/lben/wrl p91/uben p92/r/w/wrh p93/dstb/rd p94/astb p95/hldak p96/hldrq p40/ad0 p41/ad1 p42/ad2 p43/ad3 p21/so2 p22/sck2 p23/rxd1 p24/txd1 p25/asck1 v dd v ss p26/ti2/to2 p27/ti3/to3 p30/ti00 p31/ti01 p32/ti10 p33/ti11 p34/to0/a13 p35/to1/a14 p36/ti4/to4/a15 p37/ti5/to5 v pp note 1 p100/rtp0/a5 p101/rtp1/a6 p102/rtp2/a7 p103/rtp3/a8 p104/rtp4/a9 p105/rtp5/a10 p106/rtp6/a11 p71/ani1 p70/ani0 av ref av ss av dd p65/a21 p64/a20 p63/a19 p62/a18 p61/a17 p60/a16 p57/ad15 p56/ad14 p55/ad13 p54/ad12 p53/ad11 p52/ad10 p51/ad9 p50/ad8 bv ss bv dd p47/ad7 p46/ad6 p45/ad5 p44/ad4
data sheet u14527ej2v0ds00 4 p p p p pd70f3017a, 70f3017ay 121-pin plastic fbga (12 u 12 mm) p pd70f3017af1-ea6 p pd70f3017ayf1-ea6 top view bottom view nmlkjhgfedcba abcdefghjklmn 13 12 11 10 9 8 7 6 5 4 3 2 1 pin number pin name pin number pin name pin number pin name pin number pin name pin number pin name pin number pin name a1 p20 b8 p83 d2 v dd g11 p60 k13 bv dd m7 v ss a2 p15 b9 p80 d3 v ss g12 p56 l1 p104 m8 v ss a3 v ss b10 p75 d11 av dd g13 p57 l2 p105 m9 p92 a4 p13 b11 av ss d12 av dd h1 p34 l3 reset m10 p95 a5 p11 b12 av ss d13 av dd h2 p37 l4 v dd m11 p41 a6 p06 b13 p71 e1 p25 h3 p35 l5 v ss m12 p45 a7 p03 c1 p22 e2 v dd h11 p55 l6 x2 m13 p44 a8 p00 c2 p23 e3 p30 h12 p53 l7 p90 n1 p107 a9 p81 c3 v ss e11 av dd h13 p54 l8 p120 n2 p110 a10 p76 c4 p24 e12 p64 j1 v pp note l9 p93 n3 p112 a11 p73 c5 p07 e13 p65 j2 v pp note l10 p96 n4 v dd a12 p72 c6 p04 f1 p26 j3 p100 l11 bv ss n5 xt1 a13 av ss c7 p01 f2 p27 j11 p52 l12 bv ss n6 v ss b1 p21 c8 p82 f3 p33 j12 p50 l13 bv ss n7 v ss b2 p14 c9 p77 f11 p63 j13 p51 m1 p106 n8 clkout b3 v ss c10 p74 f12 p61 k1 p101 m2 p111 n9 p91 b4 p12 c11 av ss f13 p62 k2 p102 m3 p113 n10 p94 b5 p10 c12 p70 g1 p31 k3 p103 m4 v dd n11 p40 b6 p05 c13 av ref g2 p32 k11 p46 m5 xt2 n12 p42 b7 p02 d1 v dd g3 p36 k12 p47 m6 x1 n13 p43 note connect the v pp pin to v ss in the normal operating mode. remarks 1. alternate function names are omitted. the alternate functions are identical to the 100-pin plastic lqfp. 2. connect the d4 pin directly to v ss .
data sheet u14527ej2v0ds00 5 p p p p pd70f3017a, 70f3017ay pin identification a1 to a21: address bus p100 to p107: port 10 ad0 to ad15: address/data bus p110 to p114: port 11 adtrg: ad trigger input p120: port 12 ani0 to ani11: analog input rd: read asck0, asck1: asynchronous serial clock reset: reset astb: address strobe rtp0 to rtp7: real-time port av dd : analog v dd rtptrg: rtp trigger av ref : analog reference voltage r/w: read/write status av ss : analog v ss rxd0, rxd1: receive data bv dd : power supply for bus interface sck0 to sck2: serial clock bv ss : ground for bus interface scl note : serial clock clkout: clock output sda note : serial data dstb: data strobe si0 to si2: serial input hldak: hold acknowledge so0 to so2: serial output hldrq: hold request ti00, ti01, ti10, : timer input intp0 to intp6: interrupt request from peripherals ti11, ti2 to ti5 lben: lower byte enable to0 to to5: timer output nmi: non-maskable interrupt request txd0,txd1: transmit data p00 to p07: port 0 uben: upper byte enable p10 to p15: port 1 v dd : power supply p20 to p27: port 2 v pp : programming power supply p30 to p37: port 3 v ss : ground p40 to p47: port 4 wait: wait p50 to p57: port 5 wrh: write strobe high level data p60 to p65: port 6 wrl: write strobe low level data p70 to p77: port 7 x1, x2: crystal for main system clock p80 to p83: port 8 xt1, xt2: crystal for subsystem clock p90 to p96: port 9 note applies to the p pd70f3017ay only.
data sheet u14527ej2v0ds00 6 p p p p pd70f3017a, 70f3017ay internal block diagram note applies to the p pd70f3017ay only. nmi ti00, ti01, ti10, ti11 to0, to1 sio ti2/to2 ti3/to3 ti4/to4 ti5/to5 so0 si0/sda note sck0/scl note intp0 to intp6 intc csi0/i 2 c note so1/txd0 si1/rxd0 sck1/asck0 csi1/uart0 so2 si2 sck2 csi2 txd1 rxd1 asck1 256 kb pc alu cpu flash memory 8 kb ram hldrq (p96) hldak (p95) astb (p94) dstb/rd (p93) r/w/wrh (p92) uben (p91) lben/wrl (p90) wait a1 to a12 a13 to a15 (p34 to p36) a16 to a21 (p60 to p65) ad0 to ad15 cg (p40 to p47, p50 to p57) (p100 to p107, p110 to p113) p120 p114 p110 to p113 p100 to p107 p90 to p96 p80 to p83 p70 to p77 p60 to p65 p50 to p57 p40 to p47 p30 to p37 p20 to p27 p10 to p15 p00 to p07 rtp0 to rtp7 rtptrg av dd av ref av ss ani0 to ani11 adtrg clkout x1 x2 xt1 (p114) xt2 reset v dd v ss bv dd bv ss v pp bcu timer/counters 16-bit timer: tm0, tm1 8-bit timer: tm2 to tm5 dmac: 3 ch watch timer watchdog timer rtp a/d converter uart1 32-bit barrel shifter system registers multiplier 16 x 16 32 general-purpose registers 32 bits x 32 instruction queue port
data sheet u14527ej2v0ds00 7 p p p p pd70f3017a, 70f3017ay contents 1. pin functions ............................................................................................................... ................... 8 1.1 port pins ................................................................................................................... ..................................8 1.2 non-port pins ............................................................................................................... ............................11 1.3 pin i/o circuits and recommended connection of unused pins........................................................14 2. electrical specifications ................................................................................................... ... 18 3. package drawings ............................................................................................................ ......... 43 4. recommended soldering conditions................................................................................ 45
data sheet u14527ej2v0ds0 0 8 p pp p pd70f3017a, 70f3017ay 1 . pin functions 1. 1 port pins (1/3) pin name i/o pull fun c tion alternate fun c tion p00 nmi p01 i n tp0 p02 i n tp1 p03 i n tp2 p04 i n tp3 p05 intp4/adtrg p06 i ntp5 / rtptrg p07 i/o yes po r t 0 8-bit i/o port input/output c an be s pe c ified in 1-bit unit s . i n tp6 p10 si0/s d a note p11 so0 p12 s c k0/s c l note p13 s i 1 / rxd0 p14 so1/txd0 p15 i/o yes po r t 1 6-bit i/o port input/output c an be s pe c ified in 1-bit unit s . s c k1/as c k0 p20 si2 p21 so2 p22 s c k2 p23 r x d1 p24 txd1 p25 as c k1 p26 ti2/to2 p27 i/o yes po r t 2 8-bit i/o port input/output c an be s pe c ified in 1-bit unit s . ti3/to3 p30 ti00 p31 ti01 p32 ti10 p33 ti11 p34 to0/a13 p35 to1/a14 p36 ti4/to4/a15 p37 i/o yes po r t 3 8-bit i/o port input/output c an be s pe c ified in 1-bit unit s . ti5/to5 not e applies to the p pd70f3017ay only. remark pull: on-chip pull-up resistor
data sheet u14527ej2v0ds00 9 p p p p pd70f3017a, 70f3017ay (2/3) pin name i/o pull function alternate function p40 ad0 p41 ad1 p42 ad2 p43 ad3 p44 ad4 p45 ad5 p46 ad6 p47 i/o no port 4 8-bit i/o port input/output can be specified in 1-bit units. ad7 p50 ad8 p51 ad9 p52 ad10 p53 ad11 p54 ad12 p55 ad13 p56 ad14 p57 i/o no port 5 8-bit i/o port input/output can be specified in 1-bit units. ad15 p60 a16 p61 a17 p62 a18 p63 a19 p64 a20 p65 i/o no port 6 6-bit i/o port input/output can be specified in 1-bit units. a21 p70 ani0 p71 ani1 p72 ani2 p73 ani3 p74 ani4 p75 ani5 p76 ani6 p77 input no port 7 8-bit input port ani7 p80 ani8 p81 ani9 p82 ani10 p83 input no port 8 4-bit input port ani11 remark pull: on-chip pull-up resistor
data sheet u14527ej2v0ds00 10 p p p p pd70f3017a, 70f3017ay (3/3) pin name i/o pull function alternate function p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak p96 i/o no port 9 7-bit i/o port input/output can be specified in 1-bit units. hldrq p100 rtp0/a5 p101 rtp1/a6 p102 rtp2/a7 p103 rtp3/a8 p104 rtp4/a9 p105 rtp5/a10 p106 rtp6/a11 p107 i/o yes port 10 8-bit i/o port input/output can be specified in 1-bit units. rtp7/a12 p110 a1 p111 a2 p112 a3 p113 i/o yes a4 p114 input no port 11 5-bit i/o port input/output can be specified in 1-bit units. p114 is fixed as input only. xt1 p120 i/o no port 12 1-bit i/o port wait remark pull: on-chip pull-up resistor
data sheet u14527ej2v0ds00 11 p p p p pd70f3017a, 70f3017ay 1.2 non-port pins (1/3) pin name i/o pull function alternate function a1 to a4 p110 to p113 a5 to a12 p100/rtp0 to p107/rtp7 a13 p34/to0 a14 p35/ti1 a15 output yes low-order address bus used for external memory expansion p36/ti4/to4 a16 to a21 output no high-order address bus used for external memory expansion p60 to p65 ad0 to ad7 p40 to p47 ad8 to ad15 i/o no 16-bit multiplexed address/data bus used for external memory expansion p50 to p57 adtrg input yes a/d converter external trigger input p05/intp4 ani0 to ani7 input no p70 to p77 ani8 to ani11 input no analog input to a/d converter p80 to p83 asck0 p15/sck1 asck1 input yes serial clock input for uart0 and uart1 p25 astb output no external address strobe signal output p94 av dd ee positive power supply for a/d converter e av ref input e reference voltage input for a/d converter e av ss ee ground potential for a/d converter e bv dd ee positive power supply for bus interface e bv ss ee ground potential for bus interface e clkout output e internal system clock output e dstb output no external data strobe signal output p93/rd hldak output no bus hold acknowledge output p95 hldrq input no bus hold request input p96 intp0 to intp3 external interrupt request input (analog noise elimination) p01 to p04 intp4 p05/adtrg intp5 p06/rtptrg intp6 input yes external interrupt request input (digital noise elimination) p07 lben output no external data bus's low-order byte enable signal output p90/wrl nmi input yes non-maskable interrupt request input p00 rd output no read strobe signal output p93/dstb reset input e system reset input e rtp0 to rtp7 output yes real-time output port p100/a5 to p107/a12 remark pull: on-chip pull-up resistor
data sheet u14527ej2v0ds00 12 p p p p pd70f3017a, 70f3017ay (2/3) pin name i/o pull function alternate function rtptrg input yes rtp external trigger input p06/intp5 r/w output no external read/write status output p92/wrh rxd0 p13/si1 rxd1 input yes serial receive data input for uart0 and uart1 p23 sck0 p12 sck1 p15/asck0 sck2 serial clock i/o (3-wire type) for csi0 to csi2 p22 scl i 2 c serial clock i/o ( p pd70f3017ay only) p12/sck0 sda i/o yes i 2 c serial transmit/receive data i/o ( p pd70f3017ay only) p10/si0 si0 p10 si1 p13/rxd0 si2 input yes serial receive data input (3-wire type) for csi0 to csi2 p20 so0 p11 so1 p14/txd0 so2 output yes serial transmit data output (3-wire type) for csi0 to csi2 p21 ti00 external capture trigger input and external count clock input for tm0 p30 ti01 external capture trigger input for tm0 p31 ti10 external capture trigger input and external count clock input for tm1 p32 ti11 external capture trigger input for tm1 p33 ti2 external count clock input for tm2 p26/to2 ti3 external count clock input for tm3 p27/to3 ti4 external count clock input for tm4 p36/to4/a15 ti5 input yes external count clock input for tm5 p37/to5 to0, to1 pulse signal output for tm0, tm1 p34/a13, p35/a14 to2 pulse signal output for tm2 p26/ti2 to3 pulse signal output for tm3 p27/ti3 to4 pulse signal output for tm4 p36/ti4/a15 to5 output yes pulse signal output for tm5 p37/ti5 txd0 p14/so1 txd1 output yes serial transmit data output for uart0 and uart1 p24 uben output no high-order byte enable signal output for external data bus p91 v dd ee positive power supply pin e v ss ee gnd potential e remark pull: on-chip pull-up resistor
data sheet u14527ej2v0ds00 13 m m m m pd70f3017a, 70f3017ay (3/3) pin name i/o pull function alternate function wait input no control signal input for inserting wait in bus cycle p120 wrh high-order byte write strobe signal output for external data bus p92/r/w wrl output no low-order byte write strobe signal output for external data bus p90/lben x1 input - x2 - no resonator connection for main system clock - xt1 input p114 xt2 - no resonator connection for sub system clock - v pp -- pin to which high voltage is applied during program write/verify - remark pull: on-chip pull-up resistor
data sheet u14527ej2v0ds00 14 p p p p pd70f3017a, 70f3017ay 1.3 pin i/o circuits and recommended connection of unused pins the input/output circuit type of each pin and recommended connection of unused pins are shown in table 1-1. for the input/output schematic circuit diagram of each type, refer to figure 1-1. table 1-1. types of pin i/o circuits (1/2) pin alternate function i/o circuit type recommended connection of unused pins p00 nmi p01 to p04 intp0 to intp3 p05 intp4/adtrg p06 intp5/rtptrg p07 intp6 8-a input: connect to v ss output: leave open p10 si0/sda note 10-a p11 so0 26 p12 sck0/scl note 10-a p13 si1/rxd0 8-a p14 so1/txd0 26 p15 sck1/asck0 10-a p20 si2 8-a p21 so2 26 p22 sck2 10-a p23 rxd1 8-a p24 txd1 5-a p25 asck1 p26, p27 ti2/to2, ti3/to3 p30, p31 ti00, ti01 p32, p33 ti10, ti11 8-a p34, p35 to0/a13, to1/a14 5-a p36 ti4/to4/a15 p37 ti5/to5 8-a input: connect to v dd or v ss output: leave open p40 to p47 ad0 to ad7 p50 to p57 ad8 to ad15 p60 to p65 a16 to a21 5 input: connect to bv dd or bv ss output: leave open p70 to p77 ani0 to ani7 p80 to p83 ani8 to ani11 9 connect to av ss or av dd note applies to the p pd70f3017ay only.
data sheet u14527ej2v0ds00 15 p p p p pd70f3017a, 70f3017ay table 1-1. types of pin i/o circuits (2/2) pin alternate function i/o circuit type recommended connection of unused pins p90 lben/wrl p91 uben p92 r/w/wrh p93 dstb/rd p94 astb p95 hldak p96 hldrq 5 input: connect to bv dd or bv ss output: leave open p100 to p107 rtp0/a5 to rtp7/a12 26 p110 to p113 a1 to a4 5-a p114 xt1 16 input: connect to v dd or v ss output: leave open p120 wait 5 input: connect to bv dd or bv ss output: leave open av ref ee connect to av ss clkout e 4 leave open reset e 2 e x2 ee leave open (when external clock is input to x1 pin) xt2 e 16 leave open v pp C C connect to v ss
data sheet u14527ej2v0ds00 16 p p p p pd70f3017a, 70f3017ay figure 1-1. pin input/output circuits (1/2) type 2 schmitt-triggered input with hysteresis characteristics push-pull output that can be set for high-impedance output (both p-ch and n-ch off) in data output disable p-ch out v dd n-ch data output disable p-ch in/out v dd n-ch input enable data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable data output disable p-ch in/out v dd n-ch p-ch v dd pullup enable in comparator + C v ref (threshold voltage) p-ch n-ch input enable type 4 type 5 type 9 type 8-a type 5-a
data sheet u14527ej2v0ds00 17 p p p p pd70f3017a, 70f3017ay figure 1-1. pin input/output circuits (2/2) data output disable p-ch in/out v dd n-ch p-ch v dd pullup enable open drain p-ch feedback cut-off xt1 xt2 data output disable open drain p-ch in/out v dd n-ch p-ch v dd pullup enable type 10-a type 26 type 16
data sheet u14527ej2v0ds00 18 p p p p pd70f3017a, 70f3017ay 2. electrical specifications absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol conditions ratings unit v dd C0.5 to +4.6 v av dd C0.5 to +4.6 v bv dd C0.5 to +4.6 v av ss C0.5 to +0.5 v supply voltage bv ss C0.5 to +0.5 v v i1 note 1 C0.5 to v dd + 0.5 note 4 v v i2 note 2 C0.5 to bv dd + 0.5 note 4 v input voltage v i3 v pp C0.5 to +8.5 v clock input voltage v k x1, xt1, v dd = 2.7 to 3.6 v C0.5 to v dd + 1.0 note 4 v analog input voltage v ian note 3 (av dd ) C0.5 to av dd + 0.5 note 4 v analog reference input voltage av ref av ref C0.5 to av dd + 0.5 note 4 v per pin 4.0 ma total for p00 to p07, p10 to p15, p20 to p25 25 ma total for p26, p27, p30 to p37, p100 to p107, p110 to p113 25 ma total for p40 to p47, p90 to p96, p120, clkout 25 ma output current, low i ol total for p50 to p57, p60 to p65 25 ma per pin C4.0 ma total for p00 to p07, p10 to p15, p20 to p25 C25 ma total for p26, p27, p30 to p37, p100 to p107, p110 to p113 C25 ma total for p40 to p47, p90 to p96, p120, clkout C25 ma output current, high i oh total for p50 to p57, p60 to p65 C25 ma v o1 note 1 , v dd = 2.7 to 3.6 v C0.5 to v dd + 0.5 note 4 v output voltage v o2 note 2 , bv dd = 2.7 to 3.6 v C0.5 to bv dd + 0.5 note 4 v normal operating mode C40 to +85 q c operating ambient temperature t a flash memory programming mode 10 to 40 q c storage temperature t stg C40 to +125 q c notes 1. ports 0, 1, 2, 3, 10, 11, 12, reset, and their alternate-function pins. 2. ports 4, 5, 6, 9, clkout, and their alternate-function pins. 3. ports 7, 8, and their alternate-function pins. 4. be sure not to exceed the absolute maximum ratings (max. value) of each supply voltage.
data sheet u14527ej2v0ds00 19 p p p p pd70f3017a, 70f3017ay cautions 1. do not directly connect the output (or i/o) pins of ic products to each other, or to v dd , v cc , and gnd. open-drain pins or open-connector pins, however, can be directly connected to each other. direct connection of the output pins between an ic product and an external circuit is possible, if the output pins can be set to the high-impedance state and the output timing of the external circuit is designed to avoid output conflict. 2. product quality may suffer if the absolute maximum rating is exceeded even momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. the ratings and conditions indicated for dc characteristics and ac characteristics represent the quality assurance range during normal operation. capacitance (t a = 25 c, v dd = v ss = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i 15 pf i/o capacitance c io 15 pf output capacitance c o f c = 1 mhz unmeasured pins returned to 0 v 15 pf operating conditions internal operation clock frequency ( i ) supply voltage (v dd ) operating ambient temperature (t a ) 2 mhz d f xx d 17 mhz 2.7 to 3.6 v C40 to +85 c 2 mhz d f xx d 20 mhz 3.0 to 3.6 v C40 to +85 c f xt = 32.768 khz 2.7 to 3.6 v C40 to +85 c
data sheet u14527ej2v0ds00 20 m m m m pd70f3017a, 70f3017ay recommended oscillator (1) main system clock oscillator (t a = ?40 to +85 c) (a) connection of ceramic resonator or crystal resonator x1 x2 parameter symbol conditions min. typ. max. unit v dd = 2.7 to 3.6 v 2 17 mhz oscillation frequency f xx v dd = 3.0 to 3.6 v 2 20 mhz upon reset release 2 19 /f xx s oscillation stabilization time upon stop mode release note s note the typ value differs depending on the setting of the oscillation stabilization time select register (osts). caution ensure that the duty of oscillation waveform is between 45% and 55%. remarks 1. connect the oscillator as close as possible to the x1 and x2 pins. 2. do not route the wiring near broken lines. 3. sufficiently evaluate the matching between the oscillator and resonator. (b) external clock input x1 x2 high-speed cmos inverter external clock open cautions 1. connect the high-speed cmos inverter as close as possible to the x1 pin. 2. sufficiently evaluate the matching between the m m m m pd70f3017a, 70f3017ay and the high- speed cmos inverter.
data sheet u14527ej2v0ds00 21 p p p p pd70f3017a, 70f3017ay (2) subsystem clock oscillator (t a = ?40 to +85 c) (a) connection of crystal resonator xt1 xt2 parameter symbol conditions min. typ. max. unit oscillation frequency f xt 32 32.768 35 khz oscillation stabilization time 10 s remarks 1. connect the oscillator as close as possible to the xt1 and xt2 pins. 2. do not route the wiring near broken lines. 3. sufficiently evaluate the matching between the oscillator and resonator. (b) external clock input xt1 xt2 high-speed cmos inverter cautions 1. connect the high-speed cmos inverter as close as possible to the xt2 pin. 2. sufficiently evaluate the matching between the p p p p pd70f3017a, 70f3017ay and the high- speed cmos inverter.
data sheet u14527ej2v0ds00 22 p p p p pd70f3017a, 70f3017ay dc characteristics (1) operating conditions (t a = ?40 to +85 c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 pins other than below 0.7v dd v dd v v ih2 note 1 0.7av dd av dd v v ih3 note 2 0.75v dd v dd v input voltage, high v ih4 x1, xt1 (p114), xt2 0.8v dd v dd v v il1 pins other than below v ss 0.3v dd v v il2 note 1 av ss 0.3av dd v v il3 note 2 v ss 0.2v dd v input voltage, low v il4 x1, xt1 (p114), xt2 v ss 0.2v dd v v oh1 note 3 i oh = C3 ma 0.8v dd v output voltage, high v oh2 note 4 i oh = C1 ma 0.8v dd v v ol1 note 3 i ol = 1.6 ma 0.4 v v ol2 note 4 (except pins p10 and p12) i ol = 1.6 ma 0.4 v output voltage, low v ol3 p10, p12 i ol = 3 ma 0.4 v 5 p a input leakage current, high i lih v i = v dd = av dd = bv dd x1, xt1, xt2 20 p a C5 p a input leakage current, low i lil v i = 0 v x1, xt1, xt2 C20 p a output leakage current, high i loh v o = v dd = av dd = bv dd 5 p a output leakage current, low i lol v o = 0 v C5 p a i dd1 normal operation f xx = 17 mhz all peripheral functions operating 30 60 ma i dd2 halt mode f xx = 17 mhz all peripheral functions operating 10 25 ma i dd3 idle mode f xx = 17 mhz watch timer operating 48ma stop mode (subsystem oscillator, watch timer operating) 10 100 p a supply current note 5 i dd4 stop mode (subsystem oscillator stopped (xt1 = v ss )) 2 100 p a
data sheet u14527ej2v0ds00 23 p p p p pd70f3017a, 70f3017ay (1) operating conditions (t a = ?40 to +85 c, v dd = av dd = bv dd = 2.7 to 3.6 v, v ss = av ss = bv ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit i dd5 subsystem clock normal operation mode f xt = 32.768 khz (main system clock stopped) 250 600 p a supply current note 5 i dd6 subsystem clock idle mode f xt = 32.768 khz (main system clock stopped, watch timer operating) 130 360 p a pull-up resistance r l v in = 0 v 10 30 100 k : notes 1. p70 to p77, p80 to p83, and their alternate-function pins. 2. p00 to p07, p10, p12, p13, p15, p20, p22, p23, p25 to p27, p30 to p33, p36, p37, reset, and their alternate-function pins. 3. clkout, p40 to p47, p50 to p57, p60 to p65, p90 to p96, p120, and their alternate-function pins. 4. p00 to p07, p10 to p15, p20 to p27, p30 to p37, p100 to p107, p110 to p113, and their alternate- function pins. 5. the typ value of v dd is 3.3 v. the current consumed by the output buffer is not included.
data sheet u14527ej2v0ds00 24 p p p p pd70f3017a, 70f3017ay (2) operating conditions (t a = ?40 to +85 c, v dd = av dd = bv dd = 3.0 to 3.6 v, v ss = av ss = bv ss = 0 v) (1/2) parameter symbol conditions min. typ. max. unit v ih1 pins other than below 0.7v dd v dd v v ih2 note 1 0.7av dd av dd v v ih3 note 2 0.75v dd v dd v input voltage, high v ih4 x1, xt1 (p114), xt2 0.8v dd v dd v v il1 pins other than below v ss 0.3v dd v v il2 note 1 av ss 0.3av dd v v il3 note 2 v ss 0.2v dd v input voltage, low v il4 x1, x2, xt1 (p114), xt2 v ss 0.2v dd v v oh1 note 3 i oh = C3 ma 0.8v dd v output voltage, high v oh2 note 4 i oh = C1 ma 0.8v dd v v ol1 note 3 i ol = 1.6 ma 0.4 v v ol2 note 4 (except pins p10 and p12) i ol = 1.6 ma 0.4 v output voltage, low v ol3 p10, p12 i ol = 3 ma 0.4 v 5 p a input leakage current, high i lih v i = v dd = av dd = bv dd x1, xt1, xt2 20 p a C5 p a input leakage current, low i lil v i = 0 v x1, xt1, xt2 C20 p a output leakage current, high i loh v o = v dd 5 p a output leakage current, low i lol v o = 0 v C5 p a i dd1 normal operation f xx = 20 mhz all peripheral functions operating 32 64 ma i dd2 halt mode f xx = 20 mhz all peripheral functions operating 11 26 ma i dd3 idle mode f xx = 20 mhz watch timer operating 4.5 9 ma stop mode (subsystem oscillator, watch timer operating) 10 100 p a supply current note 5 i dd4 stop mode (subsystem oscillator stopped (xt1 = v ss )) 2 100 p a
data sheet u14527ej2v0ds00 25 p p p p pd70f3017a, 70f3017ay (2) operating conditions (t a = ?40 to +85 c, v dd = av dd = bv dd = 3.0 to 3.6 v, v ss = av ss = bv ss = 0 v) (2/2) parameter symbol conditions min. typ. max. unit i dd5 subsystem clock normal operation mode f xt = 32.768 khz (main system clock stopped) 250 600 p a supply current note 5 i dd6 subsystem clock idle mode f xt = 32.768 khz (main system clock stopped, watch timer operating) 130 360 p a pull-up resistance r l v in = 0 v 10 30 100 k : notes 1. p70 to p77, p80 to p83, and their alternate-function pins. 2. p00 to p07, p10, p12, p13, p15, p20, p22, p23, p25 to p27, p30 to p33, p36, p37, reset and their alternate-function pins. 3. clkout, p40 to p47, p50 to p57, p60 to p65, p90 to p96, p120, and their alternate-function pins. 4. p00 to p07, p10 to p15, p20 to p27, p30 to p37, p100 to p107, p110 to p113, and their alternate- function pins. 5. the typ value of v dd is 3.3 v. the current consumed by the output buffer is not included.
data sheet u14527ej2v0ds00 26 p p p p pd70f3017a, 70f3017ay data retention characteristics (t a = ?40 to +85 c) parameter symbol conditions min. typ. max. unit data retention voltage v dddr stop mode 1.8 3.6 v data retention current i dddr v dddr [v] 2 100 p a supply voltage rise time t rvd 200 p s supply voltage fall time t fvd 200 p s supply voltage hold time (from stop mode setting) t hvd 0ms stop release signal input time t drel 0ms data retention high-level input voltage v ihdr all input ports v ihn v dddr v data retention low-level input voltage v ildr all input ports 0 v iln v remarks 1. typ. values are reference values for when t a = 25 c. 2. n = 1 to 4 v dd setting stop mode t hvd t fvd reset (input) nmi, intp0 to intp3 (input) nmi, intp0 to intp3 (input) (when stop mode is released at rising edge) t rvd t drel v dddr v ihdr v ildr v ihdr caution shifting to stop mode and restoring from stop mode must be performed at v dd = 2.7 v min. (f xx = 17 mhz) and v dd = 3.0 v min. (f xx = 20 mhz), respectively.
data sheet u14527ej2v0ds00 27 p p p p pd70f3017a, 70f3017ay ac characteristics ac test input waveforms (1) p11, p14, p21, p24, p34, p35, p100 to p107, p110 to p113, and their alternate-function pins v dd 0 v 0.7v dd 0.3v dd 0.7v dd 0.3v dd point of measurement (2) p70 to p77, p80 to p83, and their alternate-function pins av dd 0 v 0.7av dd 0.3av dd 0.7av dd 0.3av dd point of measurement (3) p00 to p07, p10, p12, p13, p15, p20, p22, p23, p25 to p27, p30 to p33, p36, p37, reset, and their alternate-function pins v dd 0 v 0.75v dd 0.2v dd 0.75v dd 0.2v dd point of measurement (4) x1, xt1 (p114), xt2 v dd 0 v 0.8v dd 0.2v dd 0.8v dd 0.2v dd point of measurement ac test output measurement points 0.8v dd 0.4 v 0.8v dd 0.4 v point of measurement
data sheet u14527ej2v0ds00 28 p p p p pd70f3017a, 70f3017ay load conditions dut (device under test) c l = 50 pf caution if the load capacitance exceeds 50 pf due to the circuit configuration, bring the load capacitance of the device to 50 pf or less by inserting a buffer or by some other means.
data sheet u14527ej2v0ds00 29 p p p p pd70f3017a, 70f3017ay clock timing (1) operating conditions (t a = ?40 to +85 c, v dd = bv dd = 2.7 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit x1 input cycle 58.8 ns xt1 input cycle t cyx <1> 28.5 p s x1 input high-level width 26.4 ns xt1 input high-level width t wxh <2> 12.8 p s x1 input low-level width 26.4 ns xt1 input low-level width t wxl <3> 12.8 p s x1 input rise time t xr <4> 0.5 (t cyx C t wxh C t wxl ) ns x1 input fall time t xf <5> 0.5 (t cyx C t wxh C t wxl ) ns clkout output cycle t cyk <6> 58.8 ns 31.2 p s clkout high-level width t wkh <7> 0.4t cyk C 10 ns clkout low-level width t wkl <8> 0.4t cyk C 10 ns clkout rise time t kr <9> 10 ns clkout fall time t kf <10> 10 ns remarks 1. t = t cyk 2. ensure that the duty is between 45% and 55%. (2) operating conditions (t a = C40 to +85 c, v dd = bv dd = 3.0 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit x1 input cycle 50.0 ns xt1 input cycle t cyx <1> 28.5 p s x1 input high-level width 22.5 ns xt1 input high-level width t wxh <2> 12.8 p s x1 input low-level width 22.5 ns xt1 input low-level width t wxl <3> 12.8 p s x1 input rise time t xr <4> 0.5 (t cyx C t wxh C t wxl ) ns x1 input fall time t xf <5> 0.5 (t cyx C t wxh C t wxl ) ns clkout output cycle t cyk <6> 50.0 ns 31.2 p s clkout high-level width t wkh <7> 0.4t cyk C 10 ns clkout low-level width t wkl <8> 0.4t cyk C 10 ns clkout rise time t kr <9> 10 ns clkout fall time t kf <10> 10 ns remarks 1. t = t cyk 2. ensure that the duty is between 45% and 55%.
data sheet u14527ej2v0ds00 30 p p p p pd70f3017a, 70f3017ay clock timing x1, xt1 (input) clkout (output) <2> <4> <5> <1> <3> <7> <9> <10> <8> <6> (1) timing of pins other than clkout, ports 4, 5, 6, and 9 (t a = C40 to +85 q q q q c, v dd = bv dd = 2.7 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit output rise time t or <11> 20 ns output fall time t of <12> 20 ns (2) timing of pins other than clkout, ports 4, 5, 6, and 9 (t a = C40 to +85 q q q q c, v dd = bv dd = 3.0 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit output rise time t or <11> 20 ns output fall time t of <12> 20 ns 0.8v dd 0.8v dd 0.4 v 0.4 v output signal <12> <11>
data sheet u14527ej2v0ds00 31 p p p p pd70f3017a, 70f3017ay bus timing (clkout asynchronous) (t a = ?40 to +85 c, v dd = bv dd = 2.7 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit address setup time (to astb p )t sast <13> 0.5t C 15 ns address hold time (from astb p )t hsta <14> 0.5t C 15 ns address float from dstb p t fda <15> 2 ns data input setup time from address t said <16> (2 + n)t C 25 ns data input setup time from dstb p t sdid <17> (1 + n)t C 25 ns delay time from astb p to dstb p t dstd <18> 0.5t C 15 ns data input hold time (from dstb n )t hdid <19> 0 ns address output time from dstb n t dda <20> (1 + i)t C 15 ns delay time from dstb n to astb n t ddst1 <21> 0.5t C 15 ns delay time from dstb n to astb p t ddst2 <22> (1.5 + i)t C 15 ns dstb low-level width t wdl <23> (1 + n)t C 15 ns astb high-level width t wsth <24> t C 15 ns data output time from dstb p t ddod <25> 15 ns data output setup time (to dstb n )t sodd <26> (1 + n)t C 20 ns data output hold time (from dstb n )t hdod <27> t C 15 ns t sawt1 <28> n t 1 1.5t C 25 ns wait setup time (to address) t sawt2 <29> n t 1 (1.5 + n)t C 25 ns t hawt1 <30> n t 1 (0.5 + n)t ns wait hold time (from address) t hawt2 <31> n t 1 (1.5 + n)t ns t sstwt1 <32> n t 1 t C 25 ns wait setup time (to astb p ) t sstwt2 <33> n t 1 (1 + n)t C 25 ns t hstwt1 <34> n t 1ntns wait hold time (from astb p ) t hstwt2 <35> n t 1 (1 + n)t ns hldrq high-level width t whqh <36> t + 10 ns hldak low-level width t whal <37> t C 15 ns bus output delay time from hldak n t dhac <38> 0 ns delay time from hldrq p to hldak p t dhqha1 <39> (2n + 7.5)t + 25 ns delay time from hldrq n to hldak n t dhqha2 <40> 0.5t 1.5t + 25 ns remarks 1. t = 1/f cpu (f cpu : cpu operation clock frequency) 2. n: number of wait clocks inserted in the bus cycle. the sampling timing changes when a programmable wait is inserted. 3. i: number of idle states inserted after the read cycle (0 or 1). 4. the values in the above specifications are values for when clocks with a 5:5 duty ratio are input from x1.
data sheet u14527ej2v0ds00 32 p p p p pd70f3017a, 70f3017ay bus timing (clkout synchronous) (t a = ?40 to +85 c, v dd = bv dd = 2.7 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit delay time from clkout n to address t dka <41> 0 19 ns delay time from clkout n to address float t fka <42> C12 7 ns delay time from clkout p to astb t dkst <43> C12 7 ns delay time from clkout n to dstb t dkd <44> C5 14 ns data input setup time (to clkout n )t sidk <45> 15 ns data input hold time (from clkout n )t hkid <46> 5 ns data output delay time from clkout n t dkod <47> 19 ns wait setup time (to clkout p )t swtk <48> 15 ns wait hold time (from clkout p )t hkwt <49> 5 ns hldrq setup time (to clkout p )t shqk <50> 15 ns hldrq hold time (from clkout p )t hkhq <51> 5 ns delay time from clkout n to bus float t dkf <52> 19 ns delay time from clkout n to hldak t dkha <53> 19 ns remark the values in the above specifications are values for when clocks with a 5:5 duty ratio are input from x1.
data sheet u14527ej2v0ds00 33 p p p p pd70f3017a, 70f3017ay read cycle (clkout synchronous/asynchronous, 1 wait) clkout (output) a16 to a21 (output), a1 to a15 (output), note ad0 to ad15 (i/o) astb (output) dstb (output), rd (output) wait (input) t1 t2 tw t3 <41> <42> <43> <13> <44> <21> <20> <22> <18> <32> <48> <34> <33> <35> <28> <30> <29> <31> <49> <48> <49> <17> <23> <19> <43> <16> <45> <46> address hi-z <15> <44> <14> <24> note r/w (output), uben (output), lben (output) remark wrl and wrh are high level. data
data sheet u14527ej2v0ds00 34 p p p p pd70f3017a, 70f3017ay write cycle (clkout synchronous/asynchronous, 1 wait) clkout (output) a16 to a21 (output), a1 to a15 (output), note ad0 to ad15 (i/o) astb (output) dstb (output), wrl (output), wrh (output) wait (input) t1 t2 tw t3 <41> <47> <43> <13> <44> <21> <27> <18> <32> <48> <34> <33> <35> <28> <30> <29> <31> <49> <48> <49> <26> <23> <24> <14> <43> data address <25> <44> note r/w (output), uben (output), lben (output) remark rd is high level.
data sheet u14527ej2v0ds00 35 p p p p pd70f3017a, 70f3017ay bus hold clkout (output) hldrq (input) hldak (output) a16 to a19 (output), note a1 to a15 (output) ad0 to ad15 (i/o) astb (output) dstb (output), rd (output), wrl (output), wrh (output) <50> <51> <53> <38> <37> <39> <40> <50> <53> <36> th th th ti hi-z hi-z hi-z data hi-z remark r/w (output), uben (output), lben (output) <52>
data sheet u14527ej2v0ds00 36 p p p p pd70f3017a, 70f3017ay reset/interrupt timing (t a = ?40 to +85 c, v dd = bv dd = 2.7 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit reset high-level width t wrsh <54> 500 ns reset low-level width t wrsl <55> 500 ns nmi high-level width t wnih <56> 500 ns nmi low-level width t wnil <57> 500 ns n = 0 to 3 (analog noise elimination) 500 ns intpn high-level width t with <58> n = 4 to 6 (digital noise elimination) 3t + 20 ns n = 0 to 3 (analog noise elimination) 500 ns intpn low-level width t witl <59> n = 4 to 6 (digital noise elimination) 3t + 20 ns remark t = 1/f xx reset <54> <55> reset (input) interrupt <56> <57> nmi (input) <58> <59> intpn (input) remark n = 0 to 6
data sheet u14527ej2v0ds00 37 m m m m pd70f3017a, 70f3017ay tin input timing (t a = ?40 to +85 c, v dd = bv dd = 2.7 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit tin0, tin1 high-level width n = 0, 1 2t sam + 20 note ns tin high-level width t tihn <60> n = 2 to 5 3t + 20 ns tin0, tin1 low-level width n = 0, 1 2t sam + 20 note ns tin low-level width t tiln <61> n = 2 to 5 3t + 20 ns note t sam (count clock cycle) can be selected as follows by setting the prmn2 to prmn0 bits of prescaler mode register n, n1 (prmn, prmn1). when n = 0 (tm0): t sam = 2t, 4t, 16t, 64t, 256t or 1/intwti cycle when n = 1 (tm1): t sam = 2t, 4t, 16t, 32t, 128t, or 256t cycle however, when the tin0 valid edge is selected as the count clock cycle, t sam = 2t. remark t= 1/f xx <60> <61> tln remark n = 00, 01, 10, 11, 2 to 5
data sheet u14527ej2v0ds00 38 p p p p pd70f3017a, 70f3017ay csi timing (1) master mode (t a = ?40 to +85 c, v dd = bv dd = 2.7 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle time t kcy1 <62> 400 ns sckn high-/low-level width t kh1 , t kl1 <63> 140 ns sin setup time (to sckn n )t sik1 <64> 50 ns sin hold time (from sckn n )t ksi1 <65> 50 ns delay time from sckn p to son output t kso1 <66> 60 ns remark n = 0 to 2 (2) slave mode (t a = C40 to +85 c, v dd = bv dd = 2.7 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit sckn cycle time t kcy2 <62> 400 ns sckn high-/low-level width t kh2 , t kl2 <63> 140 ns sin setup time (to sckn n )t sik2 <64> 50 ns sin hold time (from sckn n )t ksi2 <65> 50 ns delay time from sckn p to son output t kso2 <66> 60 ns remark n = 0 to 2 <65> <66> <64> <62> <63> <63> remark n = 0 to 2 sckn (i/o) sin (input) son (output) input data output data
data sheet u14527ej2v0ds00 39 p p p p pd70f3017a, 70f3017ay uart timing (t a = ?40 to +85 c, v dd = bv dd = 2.7 to 3.6 v, v ss = bv ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. max. unit asckn cycle time t kcy13 <67> 200 ns asckn high-level width t kh13 <68> 80 ns asckn low-level width t kl13 <69> 80 ns remark n = 0 or 1 <68> <69> <67> asckn (input) remark n = 0 or 1
data sheet u14527ej2v0ds00 40 p p p p pd70f3017a, 70f3017ay i 2 c bus mode ( p p p p pd70f3017ay only) (t a = ?40 to +85 c, v dd = 2.7 to 3.6 v, v ss = 0 v) normal mode high-speed mode parameter symbol min. max. min. max. unit scl clock frequency f clk 0 100 0 400 khz bus-free time (between stop/start conditions) t buf <70> 4.7 C 1.3 C p s hold time note 1 t hd:sta <71> 4.0 C 0.6 C p s scl clock low-level width t low <72> 4.7 C 1.3 C p s scl clock high-level width t high <73> 4.0 C 0.6 C p s setup time for start/restart condition t su:sta <74> 4.7 C 0.6 C p s cbus compatible master 5.0CCC p s data hold time i 2 c mode t hd:dat <75> 0 note 2 C 0 note 2 0.9 note 3 p s data setup time t su:dat <76> 250 C 100 note 4 Cns sda and scl signal rise time t r <77> C 1,000 20 + 0.1cb note 5 300 ns sda and scl signal fall time t f <78> C 300 20 + 0.1cb note 5 300 ns stop condition setup time t su:sto <79> 4.0 C 0.6 C p s capacitance load of each bus line cb C 400 C 400 pf notes 1. at the start condition, the first clock pulse is generated after the hold time. 2. the system requires a minimum of 300 ns hold time internally for the sda signal in order to occupy the undefined area at the falling edge of scl. 3. if the system does not extend the scl signal low hold time (t low ), only the maximum data hold time (t hd:dat ) needs to be satisfied. 4. the high-speed mode i 2 c bus can be used in the normal-mode i 2 c bus system. in this case, set the high-speed mode i 2 c bus so that it meets the following conditions. x if the system does not extend the scl signal's low state hold time: t su:dat t 250 ns x if the system extends the scl signal's low state hold time: transmit the following data bit to the sda line prior to the scl line release (t rmax. + t su:dat = 1,000 + 250 = 1,250 ns: normal mode i 2 c bus specification). 5. cb: total capacitance of one bus line (unit: pf) remark the maximum operating frequency of the p pd70f3017ay is 17 mhz.
data sheet u14527ej2v0ds00 41 p p p p pd70f3017a, 70f3017ay i 2 c bus mode ( p p p p pd70f3017ay only) stop condition start condition restart condition stop condition scl (i/o) sda (i/o) <71> <70> <72> <73 <77> <77> <78> <78> <75> <76> <74> <71> <79> a/d converter (t a = C40 to +85 ?c, v dd = av dd = av ref = 2.7 to 3.6 v, v ss = av ss = 0 v, output pin load capacitance: c l = 50 pf) parameter symbol conditions min. typ. max. unit resolution 10 10 10 bit overall error note 1 r 0.8 %fsr conversion time t conv 5 100 p s zero-scale error note 1 r 0.4 %fsr full-scale error note 1 r 0.4 %fsr integral linearity error note 2 r 4lsb differential linearity error note 2 r 4lsb analog reference voltage av ref av ref = av dd 2.7 3.6 v analog input voltage v ian av ss av ref v av ref current ai ref 360 500 p a power supply current ai dd 13ma notes 1. excluding quantization error ( r 0.05% fsr). 2. excluding quantization error ( r 0.5 lsb) remark lsb: least significant bit fsr: full scale range
data sheet u14527ej2v0ds00 42 p p p p pd70f3017a, 70f3017ay flash memory programming mode write/erase characteristics (t a = 10 to 40 q q q q c, v dd = 3.0 to 3.6 v) parameter symbol conditions min. typ. max. unit i ddw v dd pin 67 ma write current i ppw when v pp = v pp1 v pp pin 100 ma i dde v dd pin 67 ma erase current i ppe when v pp = v pp1 v pp pin 200 ma unit erase time t er 0.2 0.2 0.2 s total erase time t ert 20 s number of rewrites note 20 times v pp0 during normal operation 0 0.2v dd v v pp supply voltage v pp1 in flash memory programming mode 7.5 7.8 8.1 v operating frequency 2 20 mhz note write/erase is regarded as one cycle. operations of the p pd70f3017a and 70f3017ay are unpredictable if flash memory is rewritten more than 20 times.
data sheet u14527ej2v0ds00 43 m m m m pd70f3017a, 70f3017ay 3. package drawings 100-pin plastic lqfp (fine pitch) (14x14) note each lead centerline is located within 0.08 mm of its true position (t.p.) at maximum material condition. item millimeters a b d g 16.00 0.20 14.00 0.20 0.50 (t.p.) 1.00 j 16.00 0.20 k c 14.00 0.20 i 0.08 1.00 0.20 l 0.50 0.20 f 1.00 n p q 0.08 1.40 0.05 0.10 0.05 s100gc-50-8eu, 8ea-2 s 1.60 max. h 0.22 + 0.05 - 0.04 m 0.17 + 0.03 - 0.07 r3 + 7 - 3 1 25 26 50 100 76 75 51 s s n j detail of lead end c d a b r k m l p i s q g f m h
data sheet u14527ej2v0ds00 44 m m m m pd70f3017a, 70f3017ay 121-pin plastic fbga (12x12) item millimeters d 12.00 0.10 e 12.00 0.10 0.10 p121f1-80-ea6 f index mark a w 0.20 a2 a1 a 1.13 e 0.80 1.48 0.10 0.35 0.06 x y 0.20 y1 1.20 zd 1.20 ze 0.08 ze a2 a1 b zd b a s s wa s wb s y1 se y 13 12 11 10 9 8 7 6 5 4 3 2 1 nmlk jhgfedcba s xab f m e d b 0.50 + 0.05 - 0.10
data sheet u14527ej2v0ds00 45 m m m m pd70f3017a, 70f3017ay 4. recommended soldering conditions the m pd70f3017a and 70f3017ay should be soldered and mounted under the following recommended conditions. for the details of the recommended soldering conditions, refer to the document semiconductor device mounting technology manual (c10535e). for soldering methods and conditions other than those recommended below, contact your sales representative. table 4-1. surface mounting type soldering conditions (1) m m m m pd70f3017agc-8eu: 100-pin plastic lqfp (fine-pitch) (14 14 mm) m m m m pd70f3017aygc-8eu: 100-pin plastic lqfp (fine-pitch) (14 14 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-2 vps package peak temperature: 215 c, time: 40 seconds max. (at 200 c or higher), count: two times or less exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) vp15-107-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) C note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period. caution do not use different soldering methods together (except for partial heating). (2) m m m m pd70f3017af1-ea6: 121-pin plastic fbga (12 12 mm) m m m m pd70f3017ayf1-ea6: 121-pin plastic fbga (12 12 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 c, time: 30 seconds max. (at 210 c or higher), count: two times or less exposure limit: 7 days note (after that, prebake at 125 c for 10 hours) ir35-107-2 partial heating pin temperature: 300 c max., time: 3 seconds max. (per pin row) C note after opening the dry pack, store it at 25 c or less and 65% rh or less for the allowable storage period.
data sheet u14527ej2v0ds00 46 p p p p pd70f3017a, 70f3017ay notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed immediately after power-on for devices having reset function. caution the p p p p pd70f3017ay contains an i 2 c bus interface circuit. purchase of nec i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips.
data sheet u14527ej2v0ds00 47 p p p p pd70f3017a, 70f3017ay regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: device availability ordering information product release schedule availability of related technical literature development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-30-67 58 00 fax: 01-30-67 58 99 nec electronics (france) s.a. madrid office madrid, spain tel: 91-504-2787 fax: 91-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. united square, singapore tel: 65-253-8311 fax: 65-250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp brasil tel: 55-11-6462-6810 fax: 55-11-6462-6829 j00.7
p p p p pd70f3017a, 70f3017ay reference document electrical characteristics for microcomputer (iei-601) note note this document number is that of the japanese version. related document p pd703014a, 703014ay, 703015a, 703015ay, 703017a, 703017ay data sheet (u14526e) v850 family and v850/sa1 are trademarks of nec corporation. m8e 00. 4 the information in this document is current as of august, 2000. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above).

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